11:53:40.614 Running procedure: 6.6.2.1
11:53:40.619 step: 1 - (6.6.2 prologue)
11:53:40.619 - Cycle power to the DUT
11:53:40.631 step: 2 - (6.6.2 prologue)
11:53:40.631 - Issue a RESET_LINK_STATES (0xC0) using link control block 0xC0
11:53:40.631 --L-> master: 1 pri: 1 fcb: 0 fcv: 0 func: RESET_LINK_STATES(0x00) 0xC0 length: 5 dest: 1024 src: 1
11:53:40.632 --P-> 05 64 05 C0 00 04 01 00 D7 F7
11:53:40.633 step: 3 - (6.6.2 prologue)
11:53:40.633 - Verify that the DUT responds with a valid link frame
11:53:40.633 - Verify that the frame uses link control block 0x00
11:53:40.634 <-P-- 05 64 05 00 01 00 00 04 27 70
11:53:40.634 <-L-- master: 0 pri: 0 fcb: 0 fcv: 0 func: ACK(0x00) 0x00 length: 5 dest: 1 src: 1024
11:53:40.635 step: 4 - (6.6.2 prologue)
11:53:40.635 - Read(0x01) fir: 1 fin: 1 con: 0 uns: 0 seq: 0x00 using link options: { control == 0xF3 }
11:53:40.635 - g60v1, All Objects
11:53:40.636 --A-> Read(0x01) fir: 1 fin: 1 con: 0 uns: 0 seq: 0x00
11:53:40.636 g60v1, All Objects
11:53:40.636 --T-> fir: 1 fin: 1 seq: 0
11:53:40.636 --L-> master: 1 pri: 1 fcb: 1 fcv: 1 func: CONFIRMED_USER_DATA(0x03) 0xF3 length: 11 dest: 1024 src: 1
11:53:40.636 --P-> 05 64 0B F3 00 04 01 00 17 D1
11:53:40.636 C0 C0 01 3C 01 06 FF 50
11:53:40.637 step: 5 - (6.6.2 prologue)
11:53:40.637 - Verify that the DUT responds with a valid link frame
11:53:40.637 - Verify that the frame uses link control block 0x00
11:53:40.639 <-P-- 05 64 05 00 01 00 00 04 27 70
11:53:40.640 <-L-- master: 0 pri: 0 fcb: 0 fcv: 0 func: ACK(0x00) 0x00 length: 5 dest: 1 src: 1024
11:53:40.640 step: 6 - (6.6.2 prologue)
11:53:40.640 - Read any number of valid responses beginning w/ sequence(0x00) and incrementing by 1 modulo 16
11:53:40.648 <-P-- 05 64 FC 44 01 00 00 04 03 D5
11:53:40.648 C0 C0 81 90 00 01 02 01 00 00 00 00 01 01 02 01 E2 97
11:53:40.648 29 00 29 00 01 01 02 01 00 04 00 04 01 01 02 01 2A 19
11:53:40.648 FF FF FF FF 01 1E 02 01 00 00 00 00 01 00 00 1E 69 7E
11:53:40.648 02 01 29 00 29 00 01 00 00 1E 02 01 00 04 00 04 42 79
11:53:40.648 01 00 00 1E 02 01 FF FF FF FF 01 00 00 14 02 01 C6 DB
11:53:40.648 00 00 00 00 01 01 00 14 02 01 29 00 29 00 01 01 C8 85
11:53:40.648 00 14 02 01 00 04 00 04 01 01 00 14 02 01 FF FF 4B 05
11:53:40.648 FF FF 01 01 00 15 02 01 00 00 00 00 01 01 00 15 AE 4A
11:53:40.648 02 01 29 00 29 00 01 01 00 15 02 01 00 04 00 04 C7 27
11:53:40.648 01 01 00 15 02 01 FF FF FF FF 01 01 00 0A 02 00 48 6C
11:53:40.648 00 13 01 01 01 01 01 01 01 01 01 01 01 01 01 01 E8 51
11:53:40.648 01 01 01 01 01 01 28 02 00 00 13 01 00 00 01 00 E3 1F
11:53:40.648 00 01 00 00 01 00 00 01 00 00 01 00 00 01 00 00 9E 0F
11:53:40.648 01 00 00 01 00 00 01 00 00 01 00 00 01 00 00 01 FE 85
11:53:40.648 00 00 01 00 00 01 00 00 01 00 00 01 00 00 01 00 DB 49
11:53:40.648 00 01 00 00 01 00 00 A0 53
11:53:40.649 <-L-- master: 0 pri: 1 fcb: 0 fcv: 0 func: UNCONFIRMED_USER_DATA(0x04) 0x44 length: 252 dest: 1 src: 1024
11:53:40.649 <-T-- fir: 1 fin: 1 seq: 0
11:53:40.676 <-A-- Response(0x81) fir: 1 fin: 1 con: 0 uns: 0 seq: 0x00 IIN(DeviceRestart, NeedTime)
11:53:40.676 g1v2, 2-Byte Start/Stop, start: 0 stop: 0
11:53:40.676 [0] - flags: 0x01
11:53:40.676 g1v2, 2-Byte Start/Stop, start: 41 stop: 41
11:53:40.676 [41] - flags: 0x01
11:53:40.676 g1v2, 2-Byte Start/Stop, start: 1024 stop: 1024
11:53:40.676 [1024] - flags: 0x01
11:53:40.676 g1v2, 2-Byte Start/Stop, start: 65535 stop: 65535
11:53:40.676 [65535] - flags: 0x01
11:53:40.676 g30v2, 2-Byte Start/Stop, start: 0 stop: 0
11:53:40.676 [0] - flags: 0x01 value: 0
11:53:40.676 g30v2, 2-Byte Start/Stop, start: 41 stop: 41
11:53:40.676 [41] - flags: 0x01 value: 0
11:53:40.676 g30v2, 2-Byte Start/Stop, start: 1024 stop: 1024
11:53:40.676 [1024] - flags: 0x01 value: 0
11:53:40.676 g30v2, 2-Byte Start/Stop, start: 65535 stop: 65535
11:53:40.676 [65535] - flags: 0x01 value: 0
11:53:40.676 g20v2, 2-Byte Start/Stop, start: 0 stop: 0
11:53:40.676 [0] - flags: 0x01 count: 1
11:53:40.676 g20v2, 2-Byte Start/Stop, start: 41 stop: 41
11:53:40.676 [41] - flags: 0x01 count: 1
11:53:40.676 g20v2, 2-Byte Start/Stop, start: 1024 stop: 1024
11:53:40.676 [1024] - flags: 0x01 count: 1
11:53:40.676 g20v2, 2-Byte Start/Stop, start: 65535 stop: 65535
11:53:40.676 [65535] - flags: 0x01 count: 1
11:53:40.676 g21v2, 2-Byte Start/Stop, start: 0 stop: 0
11:53:40.676 [0] - flags: 0x01 count: 1
11:53:40.676 g21v2, 2-Byte Start/Stop, start: 41 stop: 41
11:53:40.676 [41] - flags: 0x01 count: 1
11:53:40.676 g21v2, 2-Byte Start/Stop, start: 1024 stop: 1024
11:53:40.676 [1024] - flags: 0x01 count: 1
11:53:40.676 g21v2, 2-Byte Start/Stop, start: 65535 stop: 65535
11:53:40.676 [65535] - flags: 0x01 count: 1
11:53:40.676 g10v2, 1-Byte Start/Stop, start: 0 stop: 19
11:53:40.676 [0] - flags: 0x01
11:53:40.676 [1] - flags: 0x01
11:53:40.676 [2] - flags: 0x01
11:53:40.676 [3] - flags: 0x01
11:53:40.676 [4] - flags: 0x01
11:53:40.676 [5] - flags: 0x01
11:53:40.676 [6] - flags: 0x01
11:53:40.676 [7] - flags: 0x01
11:53:40.676 [8] - flags: 0x01
11:53:40.676 [9] - flags: 0x01
11:53:40.676 [10] - flags: 0x01
11:53:40.676 [11] - flags: 0x01
11:53:40.676 [12] - flags: 0x01
11:53:40.676 [13] - flags: 0x01
11:53:40.676 [14] - flags: 0x01
11:53:40.676 [15] - flags: 0x01
11:53:40.676 [16] - flags: 0x01
11:53:40.676 [17] - flags: 0x01
11:53:40.676 [18] - flags: 0x01
11:53:40.676 [19] - flags: 0x01
11:53:40.676 g40v2, 1-Byte Start/Stop, start: 0 stop: 19
11:53:40.676 [0] - flags: 0x01 value: 0
11:53:40.676 [1] - flags: 0x01 value: 0
11:53:40.676 [2] - flags: 0x01 value: 0
11:53:40.676 [3] - flags: 0x01 value: 0
11:53:40.676 [4] - flags: 0x01 value: 0
11:53:40.676 [5] - flags: 0x01 value: 0
11:53:40.676 [6] - flags: 0x01 value: 0
11:53:40.676 [7] - flags: 0x01 value: 0
11:53:40.676 [8] - flags: 0x01 value: 0
11:53:40.676 [9] - flags: 0x01 value: 0
11:53:40.676 [10] - flags: 0x01 value: 0
11:53:40.676 [11] - flags: 0x01 value: 0
11:53:40.676 [12] - flags: 0x01 value: 0
11:53:40.676 [13] - flags: 0x01 value: 0
11:53:40.676 [14] - flags: 0x01 value: 0
11:53:40.676 [15] - flags: 0x01 value: 0
11:53:40.676 [16] - flags: 0x01 value: 0
11:53:40.676 [17] - flags: 0x01 value: 0
11:53:40.676 [18] - flags: 0x01 value: 0
11:53:40.676 [19] - flags: 0x01 value: 0
11:53:40.678 steps: 1 to 4
11:53:40.678 - Prepare a class 0 request using Qualifier Code 0x06 and a link control block 0xD3
11:53:40.678 - Modify the frame so it begins with modified start octets {0x09, 0x64}
11:53:40.678 - Modify the CRC of the data link layer header so the CRC is correct for the invalid start octet
11:53:40.679 --P-> 09 64 0B D3 00 04 01 00 92 21
11:53:40.679 C0 C0 01 3C 01 06 FF 50
11:53:40.680 step: 5
11:53:40.680 - Wait for 3000 milliseconds
11:53:43.682 step: 6
11:53:43.682 - Verify that no link layer frames are received
11:53:44.683 frame receive timeout
11:53:44.684 steps: 7 to 9
11:53:44.684 - Prepare a class 0 request using Qualifier Code 0x06 and a link control block 0xD3
11:53:44.684 - Modify the frame so it begins with modified start octets {0x05, 0xFF}
11:53:44.684 - Modify the CRC of the data link layer header so the CRC is correct for the invalid start octet
11:53:44.685 --P-> 05 FF 0B D3 00 04 01 00 85 76
11:53:44.685 C0 C0 01 3C 01 06 FF 50
11:53:44.686 step: 10
11:53:44.686 - Wait for 3000 milliseconds
11:53:47.686 step: 11
11:53:47.686 - Verify that no link layer frames are received
11:53:48.687 frame receive timeout
11:53:48.689 steps: 1 to 4
11:53:48.689 - Prepare a class 0 request using Qualifier Code 0x06 and a link control block 0xD3
11:53:48.689 - Modify the frame so it begins with modified start octets {0x01, 0x64}
11:53:48.689 - Modify the CRC of the data link layer header so the CRC is correct for the invalid start octet
11:53:48.689 --P-> 01 64 0B D3 00 04 01 00 02 91
11:53:48.689 C0 C0 01 3C 01 06 FF 50
11:53:48.690 step: 5
11:53:48.690 - Wait for 3000 milliseconds
11:53:51.690 step: 6
11:53:51.690 - Verify that no link layer frames are received
11:53:52.691 frame receive timeout
11:53:52.692 steps: 7 to 9
11:53:52.692 - Prepare a class 0 request using Qualifier Code 0x06 and a link control block 0xD3
11:53:52.692 - Modify the frame so it begins with modified start octets {0x05, 0xAA}
11:53:52.692 - Modify the CRC of the data link layer header so the CRC is correct for the invalid start octet
11:53:52.693 --P-> 05 AA 0B D3 00 04 01 00 49 02
11:53:52.693 C0 C0 01 3C 01 06 FF 50
11:53:52.694 step: 10
11:53:52.694 - Wait for 3000 milliseconds
11:53:55.695 step: 11
11:53:55.695 - Verify that no link layer frames are received
11:53:56.696 frame receive timeout
11:53:56.696 Passed procedure: 6.6.2.1